in a few words from the wikipedia article: a CPU cache used memory management hardware to improve the speed of virtual address translation.(wikipedia).
Much information comes from this article.
The idea is that CPUs keep an associative memory to cache page table entries (PTEs) of virtual pages which were recently accessed.
When the CPU must access virtual memory, it looks up in the TLB for a number corresponding to the entry to obtain.
If an entry was found (a TLB hit), then the CPU can use the value of of the PTE which accessed and calculate the physical address.
In case it was not found (a TLB miss), then depending on the architecture, the miss is handled:
- through hardware, then the CPU tries to walk the page table and find the correct PTE. if one is found the TLB is updated, if none is found then the CPU raises a page fault, which is then treated by the operating system.
- through software, then the CPU raises a TLB miss fault. The operating system intercepts the miss fault and invoke the corresponding handler, which walks the page. if the PTE is found, it is marked present and the TLB is updated. if it not present, the page fault handler is then in charge.
Mostly, CISC (IA-32) use hardware, while RISC (alpha) use software. IA-64 uses an hybrid approach because the hardware approach is faster but less flexible as the software one.
Replacement policy
If the TLB is full, some entries must be replaced. For this depending on the miss handling strategy, different strategies and policy exist:
- Least recently used (aka LRU)
- Not recently used (aka NRU)
Ensure coherence with page Table
Another issue is to keep the TLB coherent with the page table it represents.
